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PDP-1 COMPUTER 
ELECTRICAL ENGINEERING DEPARTMENT 
MoX.T, 
CAMBRIDGE, MASSACjbsETTS 02139 



PDP-35 
PDP-1 INSTRUCTION LIST 



August 7, 1968 



INSTRUCTION 


PAGE 


a am 


56 


add 


3 


a dm 


3 


and 


5 


arq 


50 


asc 


42 


bam 


56 


bpt 


54 


cac 


42 


cal 


8 


calcomp 


36A 


cbs 


40 


ckn 


36 


cks 


45 


cla 


18 


clc 


20 


elf 


18 


cli 


17 


clo 


16 


cma 


18 


cmi 


18 


dac 


i 


dam 


56 


dap 


1 


dba 


32 


dec 


33 


dia 


32 


die- 


2 


dip 


2 


div 


4 


dpy 


29 


dra 


34 


dsc 


42 


dsm 


54 


dzm 


2 


eem 


43 


esm 


39 



INSTRUCTION 


PAGE 


hit 




18 


lam 




55 


idx 




4 


lor 




5 


lot 




21 


isp 




6 


Jda 




7 


jdp 




8 


jmp 




7 


Jsp 




7 


lac 




JL 


lal 




19 


lat 




17 


law 




9 


lea 




37 


lei 




37 


lem 




44 


lia 




19 


light 


pen 


31 


lio 




2 


lpf 




57 


Ism 




39 


Ixr 




2 


microprogram 


58 


microtape 


47 


mul 




3 


nam 




55 


nop 




19 



opr 

ppa 
ppb 



17 

26 
26 



INSTRUCTION 


PAGE 


INSTRUCTION 


PAGE 


ral 


10 


spq 


16 


rar 


10 


stf 


18 


rbt 


35 


sub 


3 


rcl 


11 


swp 


20 


rcr 


11 


sza 


14 


rer 


37 


szf 


16 


ril 


11 


szm 


16 


rir 


10 


szo 


15 


rpa 


22 


szs 


15 


rpb 


24 






rpf 


57 


tyi 


28 


rrb 


25 


tyo 


27 


sad 


6 


wat 


54 


sal 
sar 
sas 


10 

10 

6 


xct 
xor 


13 

5 


scl 


12 






scr 


12 






sdl 


30 






sft 


9 






sil 


11 






sir 


11 






skp 


14 






sma 


14 






snl 


15 






spa 


14 






spi 


15 







PDP-1 INSTRUCTION LIST 

This list includes the title of the instruction, the normal 
execution time {l.e*, the time with no indirect address*), the 
mnemonic code of the instruction, the operation code number, and 
the description of the instructions operation. In the following 
list, the Accumulator is abbreviated as AC, the In-Out Register as 
10, and the contents of a register as C(K Thu3, C(Y) indicates 
the contents of memory at Address Y, C(AC), the contents of the 
Accumulator: and 0(10). the contents of the In-Out Register „ 

I. mSKOEY REFERENCE INSTRUCTIONS 
A. Information Transfer 

io Load Accumulator (iO^sec) 
lac Y Operation Code 20 

The C(Y) are placed in the Accumulator,, The C(Y) 
are unchanged . The original C(AC) are lost. 
2o Deposit Accumulator (iOMsec) 
dac Y Operation Code 24 

The C(AC) replace the C(Y) in the memory. The C(AC) 
are left unchanged by this instruction. The original 
C(Y) are lost. 
3* Deposit Address Part (iO/tsec) 
dap Y Operation Code 26 

Bits 6 through 1? of the accumulator replace the corres- 
ponding digits of memory register Y. The C(AC) are unchanged 
as are the contents of bits through 5 of y, The 
original contents of bits 6 through 17 of Y are lost. 



* Add 5 microseconds for each indirect address level. 
£& See additional notes. 



-2- 

4 Deposit Instruction Part (10,4 sec) 
dip Y Operation Code 30 

Bits through 5 of the Accumulator replace the 
corresponding digits of memory register Y. The 
CUc) are unchanged as are the bits 6 through 17 
of Yo The original contents of bits through 5 
of Y are lost* 

5» Load. In-Out Register (lO^sec) 
lio Y Operation Code 22 

The C(y) are placed in the In~Out Register, The 
C(Y) are unchanged* The original C('IO) are lost. 

6* Deposit In-Out Register (l0/£ sec) 
dio Y Operation Code 32 

The C(I0) replace the C(Y) in memory , The C(lO) 
are unaffected by this instruction. The original 
C(Y) are lost. 

7« Deposit Zero in Memory (lO-^sec) 
dzm Y Operation Code 3^ 

Clears (sets equal to plus zero) the C(Y). 

8o Load Index Register (lO^see) 
lxr Y Operation Code 12 

The C(Y) are placed in the Index Register . 

The C(Y) are unchanged- The original C(XR) are lost 



Bo Arithmetic Instructions 
lo Add (iO /*see) 

add Y Operation Code 40 

The sijon of the c(y) and the C(AC) replace the cUcK 
The C(Y) are unchanged. The addition is performed 
with one's complement arithmetic „ If the sum of 
two like-signed numbers yields a result of the 
opposite sign, the overflow flip-flop will be set 
(see szo instruction), a result of minus zero is 
changed to plus zero. Note that (-0)+(-0)«+0 and 
overflow is turned on« 

2, Add to Memory (±0 h sec) 
adm Y Operation Code 36 

The sum of the C(y) and the C(AC) replace both 
the C(Y) and the C(AC). Otherwise, it is similar 
to ^ Li@ add instruction. 

3» Subtraction (10 ^ sec) 
sub Y Operation Code 42 

The C(AC) minus the C(Y) replace the C(AC), The 
C(Y) are unchanged* The subtraction is performed 
using one"s complement arithmetic When two unlike- 
signed numbers are subtracted, the sign of the 
result must agree with the sign of the original 
Accumulator, or the overflow flip-flop will be set 
(see szo instruction)* A result of minus zero can 
exist in one instance only, (-0)-(+0)=*(-0h 

4 Multiply (14 to 25 /(Sec) 
mul Y operation Code 54 

The product of the C(AC) and the C(Y) is formed in 
the AC and 10 registers « The sign of the produce is 
in the AC sign blto 10 bit 17 also contains the sign 
of the product. The magnitude of the product is the 
34-bit string from AC Bit 1 through 10 bit 16. The 
C(Y) are not affected by this Instruction If the 
entire product results in a minus zero, It Is changed 



-4- 



to a plus zero. The variation in execution time is 
caused by the number of one 3 s in C(Y) 



product* 




5. Divide (30 to 40>(sec, except on overflow, 12* sec) 
div Y Operation Code 56 

The dividend must be in the AC and 10 registers in 
the form indicated in the instruction, mul. 10 
bit I? is ignored o The divisor is the C(Y). At 
the quotient and the C(I0) are the remainder. The 
sign of the remainder (in 10 bit zero) is the sign 
of the dividend. The instruction that follows a 
div instruction will be skipped unless an overflow 
occurs. The C(y) are not affected by this instruction. 
If the remainder of quotient result in minus zero, 
that value is changed to plus zero.. If the magnitude 
of the high order part of the dividend is equal to 
or greater than the magnitude of the divisor, an 
overflow is indicated. In this case, the instruction 
following the div is not skipped. The original 
C(AC) and C(l0) are restored The overflow flip-flop 
is not affected. 



AC 



10 



li 



a 



j 



a quo-Giens ^remainder 
quotient sign dividend sign 

Index (10 A sec) 

idx Y Operation Code 44 

C(Y) + 1 replace the C(Y) and the C(AC)„ The previous 
C(AC) are lost. Overflow is not indicated. If 
the original C(Y) equals the integer, minus one i-l), 
the result after indexing is plus zero. 




-5- 

Logical Instructions 
io Logical MD (lO^sec) 
and Y Operation Code 02 

The bits of C(Y) operate on the corresponding bits 
of the Accumulator to form the logical AND. The 
result is left in the Accumulator* The C(Y) are 
unaffected by this instruction. 

Logical AND Table 
AgJjit Y bit 



1 

1 Q 
1 1 

2o Exclusive OR ( 10 ^ sec) 
xor Y Operation Code 06 

The bits of C(Y) operate on the corresponding biti 
of the Accumulator to form the exclusive OR. The 
result is left in the Accumulator . The C(Y) are 
unaffected by this instruction* 

Exclusive OR table 
AC *4£ Y bit Result 

° o 

x ± 

1 ! 

1 10 

- Inclusive OR (10 M. sec) 

ior Y Operation Code 04 

The bits of C(Y) operate on the ^orrespondir^ bits 
of the Accumulator to form the inclusive OF* The 
result is left in the Accumulator,, The O r AC) are 
unaffected by this instruction,, 

Inclusive OR table 
AS-frU Y bit Result 



! ± 

1 1 
1 11 



D* Decision-Making Instructions 

io tkip if Accumulator and Y Differ (10 4 sec) 
sad Y Operation Code 50 

The C(Y) are compared with C(AC)* If the two 
numbers are different, the Program Counter is 
indexed one extra position and the next instruction 
in the sequence is skipped. The C(AC) and the 
C(Y) are unaffected by this operation. 

2* Skip if Accumulator and Y are the Same (lOAsecj 
sas Y Operation Code 52 

The C(Y) are compared with C(ACh If the two 
numbers are identical, the Program Counter is 
indexed one extra position and the next instruction 
in the sequence is skippedc The C(AC) and the C(Y) 
are unaffected by this operation 

3° Index and Skip if Positive (iCMsec) 
isp Y Operation Code 46 

The C(Y) +1 replace the C(Y) and the C(AC)» The 
previous C(AC) are lost. If, after the addition 
the Accumulator is positive, the Program Counter 
is advanced one extra position and the next 
instruction in the sequence is skipped * Overflow 
ifi not indicated. If the original C(Y) equals the 
integer, minus one (-1), the result after indexing 
Is plus zero and the skip takes place- 



~7~ 

So Transfer Instructions 
1« Jump (5 4 sec) 

Jmp Y Operation Code 60 

The next instruction executed will be taken from 
Memory Register Y* The Program Counter is reset 
to Memory Address Y* The original contents of the 
Program Counter are losto 

2„ Jump and Save Program Counter (5 M sec) 
jsp Y Operation Code 62 

The contents of the Program Counter are transferred 
to bits 6 through 17 of the Accumulator. The state 
of the overflow flip-flop is transferred to bit zero^ 
the condition of the Extend flip-flop to bit 1, and 
the contents of the Extended Program Counter to bits 
3 j 4, and 5 of the AC, When the Transfer of the ?Q 
to the AC takes place* the Program Counter holds the 
address of the instruction following the jsp- The 
Program Counter is then reset to Address Y» The 
next instruction executed will be taken from Memory 
Register Y. The original C(AC) are lost* 

3» Jump and Deposit Accumulator (iO /(sec) 
jda Y Operation Code 17 

The contents of the AC are deposited in Memory 
Register Y» The contents of the Program Counter 
(holding the address of the instruction following 
the jda instruction) are transferred to bits 6 
through 17 of the AC. The state of the overflow 
flip-flop is transferred to bit zero, the condition 
of the Extend flip-flop to bit 1, and the contents 
of the Extended Program Counter to bits 3, 4, and 
5 of the AC, The next instruction executed is 
taken from Memory Register Y+lo The jda instruction 
requires that the indirect bit be a one, but 
indirect addressing does not occur* The instruction 
is equivalent to the instruction dac Y followed 
by jsp Y+l. 



-8- 



4. Jump and Deposit Program Counter (10 # sec) 
jdp Y Operation Code 14 

The contents of the Program Counter (holding the 
address of the instruction following the jdp) 
are deposited in hits 6 through 17 of the Memory 
Register Y* The original contents of the AC 
remain in the AC unchanged «, The state of the 
overflow flip-flop is transferred to bit 
zero, the condition of the Extend flip-flop 
to hit 1, and the contents of the Extended 
Program Counter to bits 3 3 k, and 5 of 
the Memory Register Y* The next instruction 
executed is taken from Memory Register Y-kU 

5. Call Subroutine (lO^sec) 
cal Y Operation Code ±6 

The address part of the instruction, Y, is 
ignored c The contents of the AC are deposited 
in the Memory Register 100 of core 0. The 
contents of the Program Counter (holding the address 
of the instruction following the cal) are 
transferred to bits 6 through 17 of the AC 
The state of the overflop flip-flop is 
transferred to bit zero, the condition of 
the Extend flip-flop to bit i, and the 
contents of the Extended Program counter to 
bits 3, 4, and 5 of the AC. The next 
instruction executed is taken from Memory 
Register 101* (See above*) The cal instruction 
requires that the indirect bit be zero* The 
instruction may be used as part of a master 
routine to call subroutines,, 



££ 4i&g£§E£M Instructions, 

1* Load Accumulator with H (5 sec) 
law N Operation Code 70 

The number in the memory address bits of the 
instruction word is placed in the Accumulator* If 
the indirect- address bit (bit 5) is a one (i), 
(-H)is put in the Accumulator. 

A« Shift Group (5 sec) 
sft Operation Code 66 

This group of instructions will rotate or shift the 
Accumulator and/or the In-Gut "Register* When the two 
registers operate combined, the In-Out Register is 
considered to be an 18-bit magnitude extension of the 
right end of the Accumulator. 

a. Rotate is a non-arithmetic cyclic shift- That 
is, the two ends of the register are logically 
tied together and information is rotated as 
though the register were a ring. 

b. Shift is an arithmetic operation and is, in 
effect, multiplication of the number in the 
register hy 2~^, where N is the number of 
shifts: plus is left and minus is righto 

As bits are shifted out from one end of 

a register they are replaced at the other 

end by ones if the number is negative and zeroes 

if the number is positive • The sign bit 

is not shifted. The number of shift or 

rotate steps to be performed (H) 

is indicated by the number of one's (l J s) 

in bits 9 through 17 of the instruction 

word. Thus, Rotate Accumulator Right 

nine times is &7VIXL< A shift or rotate of one 

place can be indicated nine different ways. The 

usual convention is to use the right end 

of the instruction word, (rar 1 ==671001) 



-10- 

!• Rotate Accumulator Right (5 # sec) 
rar N Operation Code 671 

Rotates the bits of the Accumulator right K positions-, 
where N is the number of one's (1's) in bits 9 
through 17 of the instruction word. 

2. Rotate Accumulator Left (5 #sec) 
ral N Operation Code 661 

Rotates the bits of the Accumulator left H positions, 
where N Is the number of one s s (l»s) in bits 9 
through 17 of the instruction word* 

3. Shift Accumulator Right (5#aec) 
sar N Operation Code 6J5 

Shifts the contents of the Accumulator right N 
positions j wheie N is the number of one's (l»s) 
in bits 9 through 17 of the instruction word. As 
bits are shifted out from the right end of the AC 
they are replaced at the left end by ones if the 
number is negative and zeroes If the number is 
positive. The sign bit Is not shifted, 

4o Shift Accumulator Left (5/isec) 
sal N Operation Code 665 

Shifts the contents of the Accumulator left fi positions, 
where N is the number of one's (1 s s) in bits 9 
through 17 of the instruction word. As bits are 
shifted out from the left md of the AC they are 
replaced at the rl^it end by ones if the number 
Is negative and zeroes If the number is positive, 
The sign bit is not shifted. 

5. Rotate In-Out Register Right (5//sec) 
*»£*» 29 Operation Code 672 

Rotates the bits of the In-Out Register right N 
positions, where .N is the number of one's (l«s) 
In bits 9 through 17 of the Instruction word. 



-11- 



60 Rotate In-Out Register Left- (5^ sec) 
ril N Operation Code 662 

Rotates the bits of the In-Out Register left N 
positions, where N is the number of one 3 s (l»s) 
in bits 9 through 17 of the instruction word. 
7. Shift In-Out Register Right ,5/fsec) 
sir N Operation Code 676 

Shifts the contents of the In-Out Register right M 
positions, where N is the number of one«s (l J s) in 
bits 9 through i7 of the instruction word. As 
bits are shifted out from the right end of the 
10 they are replaced at the left end by ones if 
the number :ls negative and zeroes if the number 
is positive . The sign bit is not shifted. 
80 Shift In-Out Register Left (5a see) 
sil $ Operation Code 666 

Shifts the contents of the In-Out Register left N 
positions, where N is the number of one's (i«s) 
in bits 9 through 17 of the instruction word. 
As bits are shifted out from the left end of the 
10 they are replaced at the right end by ones if 
the number is negative and zeroes if the number 
is positive. The sign bit is not shifted. 
9* Rotate Accumulator and In-Out Right (5 M see) 
rcr N Operation Code 673 

Rotates the bits of the combined registers right in 
a single ring N positions, where N is the number 
of one's (i«s) in bits 9 through 17 of the instruction 
word. 
10 o Rotate Accumulator and In-Out Left (5#see) 
rcl N Operation Code 663 

Rotates the bits of the combined register left in 
a single ring N position, where N is the number of 
one's (l»s) in bits 9 through 17 of the instruction 
word. 



ll s Shift Accumulator and In-Out Right (5 ^sec) 

sop N Operation Code 677 

Shifts the contents of the combined register right 

N positions, where N is the number of one's (i's) 

in bits 9 through 17 of the instruction word. 

As bits are shifted out from the right end of the 

10 they are replaced at the left end of the AC 

by ones if the number is negative and zeroes if the 

number is positive. The sign bit is not shifted , 

Shifts the contents of the combined registers 
left u positions, where N is the number of one's 
(l's) in bits 9 through 17 of the instruction word. 
As bits are shifted out from the left end of the 
AC they are replaced at the right end of the 10 
by ones if the number is negative and zeroes if the 
number is positive. The sign bit is not shifted. 



-13- 

F« Miscellaneous 

1. Execute (5 fAsec plus time of Instruction executed) 
xct Y Operation Code 10 

The instruction located in register Y is executed. 
The Program Counter remains unchanged (unless a 
Jump or skip were executed), If a skip instruction 
Is executed (by xct Y), depending on the skip 
condition either the Program Counter is advanced 
one extra position and the next instruction in 
the sequence (after- the xct instruction) 
is skipped or the Program Counter remains unchanged 
and the next Instruction In the sequence is executed. 
Execute may be indirectly addressed, and the 
instruction being executed may use indirect addressing, 
An xct Instruction may execute other xct commands. 



-14- 

B* Skip Group (5 *see) 
skp Operation Code 64 

This group of instructions senses the state of various 
flip-flops and switches in the machine . The address 
portion of the instruction selects the particular function 
to be sensed. All members of this group have the same 
operation code The in. true t ions in the Skip Group may 
be combined to form the inclusive OR of the separate 
skips * Thus, if Address 3000 is selected, the skip 
would occur if the .overflow flip-flop equals (zero) 
or if the In-Out Register is positive, 

a. The combined instruction would still take 5 
microseconds • 

b. The intents of any skip instruction can be 
reversed by making bit 5 (normally the indirect 
address bit) equal to one (l). For example, 
the skip oh Zero Accumulator instruction, with 
bit 5 equal to one (i), becomes Bo Not Skip 

on Zero Accumulator, 

lo Skip on Zero Accumulator (5>$sec) 
ssa Address 0100 

If the Accumulator is equal to plus zero (all 
bits zre zero), the Program Counter is advanced 
one extra position and the next instruction in 
the sequence is skipped* 

2„ Skip on Plus Accumulator (5*fsec) 
spa Address 0200 

If the sign bit of the Accumulator is zero (0), 
the Program Counter is advanced one extra position 
and the next instruction in the sequence is skipped ♦ 

3. Skip on Minus Accumulator (5* sec) 
sma Address 0400 

If the sign bit of the Accumulator is a one (l)l 
the Program Counter is advanced one extra position 
and the next instruction in the sequence is 
skipped. 



—15- 

4. Skip on ftero Overflow (5 sec) 
szo Address 1000 

If the overflow flip-flop is a zero (0), the Program 
Counter is advanced one extra position and the 
next instruction in the sequence will be skipped. The 
overflow flip-flop is cleared by the Instruct on. This 
flip-flop is set only by an addition or subtraction 
that exceeds the capacity of the accumulator, (see 
definition of add and subtract Instructions.) 
The overflow flip-flop is not cleared by arithmetic 
operations which do not cause an overflow. Thus, a 
whole series of arithmetic operations can be checked 
for correctness by a single szo. The overflow 
flip-flop Is also cleared by the "start" switch* 

5c Skip on Plus In-Out Register (5 sec) 
spl Address 2000 

If the sign bit of the In-Out register is zero, 
the Program Counter is indexed one extra position* 
and the next instruction in sequence Is skipped . 

6. Skip on Non-Zero In-Out Register (5 sec) 
sni Address 4000 

If the In-Out Register Is not equal to plus zero 
(at least one bit is a one)* the Program Counter is 
advanced one extra position and the next instruction 
in the sequence is skipped. 

?• Skip on Zero Switch (5 sec) 

szs Address 001Q, 0020, 0030, ... 0070 

If the selected Sense Switch Ib zer© the Program 
Counter is advanced one extra position and the 
next Instruction in the sequence will be skipped. 
Address 10 senses the position of Sense Switch 1, 
Address 0020, Switch 2, etc. Address 0070 senses all 
the switches. If Address 0070 is selected all 6 
switches must be zero (0) to cause the skip. The 
Instruction to skip on zero senee switch I would 
be szs 10, for sense switch 2, szs 20, etc. 



-16- 

80 Skip on Zero Program Flag (5/^ sec) 
szf Addresses 0001 to 0007 

If the selected program flag is a zero, the 
Program Counter is advanced one extra position 
and the next instruction in the sequence will 
be skipped. Address 0001 selects Program Flag 1, 
etc. Address 0007 selects all six program 
flags. All six must be zero to cause the skip. 
The instruction to skip on zero program flag 
1 would be szf 1, for program flag 2, szf 2, etc. 

The following skip group instructions are extended instructj 



They are defined to represent the or-ing of existing skip ins true 

9. Skip on Zero or Minus Accumulator (5 A sec) 
szm 

If the sign bit of the Accumulator is a one (l) 
or if the Accumulator is <?tqual to plus zero 
(all bits are zero), the Program Counter is 
advanced one extra position and the next 
instruction in the sequence is skipped. This 
represents the or-ing of sza and sma. 

10. Skip on Positive Quantity (5><{sec) 
spq 

If the Accumulator is not equal to plus zero 
(all bits are zero) and if the sign bit of 
the accumulator is not a one [l), the Program 
Counter is advanced one extra position and 
the next instruction in the sequence is skipped. 
This represents the or-ing of sza i and siaa i. 

11. Clear the Overflow Flip-flop (5-^ sec) 
clo 

The overflow flip-flop is set only by addition 
or subtraction that exceeds the capacity of 
the AC. The overflow flip-flop is cleared by 
the in true t ion szo: it is not cleared by 
any arithmetic operations. This instruction 

clears the overflow flip-flop and then proceeds 
to the next instruction in the sequence. This 
reoresents the or-ing of szo, sma, spa, and 1. 



:tions. 



-17- 



Operate Group (5Xsec) 
opr Operation Code 76 



This instruction group performs miscellaneous operations 
on various Central Processor Registers, The address 
portion of the instruction specifies the action to be 
performed. The Instructions in the Operate Group can 
be combined to give the union of the functions. For 
example, the instruction opr 3200 will clear the AC, 
put the contents of the Text Word into the AC, and 
complement the AC* 

a. The combined instruction would still take 5 
microseconds * 

b. The order of operate class instructions is: 

EFFECT 0«*AC TW-*AC,stf AC-»AC 0-^MB lO*MB(la±) AO*MB(Ua) MB-*XO 
0-MO elf o-*UN (lai) OlO(lia) MB*AC(lal) (lia) 

X0*XO 

7 8 9 10 l t 2 
TIMS Time pulses of this instruction TPs of next instruction 

1* Clear the In-Out Register (5^sec) 
cli Address 4000 

Clears (set equal to plus zero) the In-Out Register., 

2. Load the Accumulator from the Test Word (5^sac) 
lat Address 2000 

Forms the inclusive OR of the C(AC) and the contents 
of the Test Word* This Instruction is usually 
combined with Address 0200 (Clear Accumulator), so 
that C(AC) will equal the contents of the Test Word 
Switches. (Thus, lat Is defined as 762200 initially 
in certainly symbol table and ID symbol table. ) 



-18- 

3« Complement the In-Out Register (5 Msec) 
cm! Address 0100 

Complements (changes all ones to zeroes and all 
zeroes to ones) the contents of the In-Out Register, 

4* Complement the Accumulator (5 4 sec) 
cma Address 1000 

Complements (changes all ones to zeroes and all 
zeroes to ones) the contents of the Accumulator. 

5- Halt 

hit Address 0400 

Stops the computer. When the computer is in 
Time-Sharing, this instruction is treated as 
an illegal instruction when executed. 

6. Clear the Accumulator {5 ft sec) 
cla Address 0200 

Clears (sets equal to plus zero) the contents 
of the Accumulator. 

7. Clear Selected Program Flag (5>£sec) 
elf Address 0001 to 0007 

Clears the selected Program Flag. Address 0001 
clears Program Flag 1, 0200 clears Program Flag 2, 
etc. Address 0007 clears all program flags. Thus, 
the instruction to clear Program Flag 1 is elf 1, 
for Program Flag 2, elf 2, etc. 

8. Set Selected Program Flag (5-^sec) 
stf Address 0011 to 0017 

Sets the select porgram flag. Address 0011 sets 
Program Flag 1: 0012 sets Program Flag 2, etc. 
Address 0017 sets all program flags. Thus, if 
stf is defined as 76OOIO, the instruction to set 
Program Flag 1 is stf 1, for Program Flag 2, 
stf 2, etc* (Stf is initially defined in 

CERTAINIA symbol table and ID symbol table as 
760010.J 



-19- 

9* No Operation (5 /(sec) 
nop Address 0000 

The state of the computer is unaffected by this 
operation, and the Program Counter continues in 
sequence • 

10 10. Load the Accumulator from the In-Out Register (5 sec) 
lai Address 0040 

This instruction copies the contents of the in-out 
register into the Accumulator. It happens after all 
normal operate class options. If the computer is 
stopped at the end of this instruction, the Memory 
Buffer Register will contain zero, and the old 
contents of the Accumulator }*ill he shown a (See 
the order of implementation of the operation class 
instructions at the beginning of this section* ) 

Up load the In-Gut Register from the Accumulator (5 sec) 
lia Address 0020 

This instruction copies the contents of the 
Accumulator into the in-out register- It happens 
after all normal operate class options. If the 
computer is stopped at the end of this instruction* 
the Memory Buffer Register will contain zero, and 
the old contents of the In-Out Register will be 
shown . (See the order of implementation of the 
ope^fat^ 2 lass instructions at the beginning of 
this section* ) 



-dO- 

The following operate group instructions are extended instructions; 
they are defined to represent the or-ing of existing operate instructions 

12. Swap Accumulator with the In-Out Register (5^ sec) 
swp 

This instruction is the combination of lia and iai. 
It copies the contents of the Accumulator into the 
In-Out Register and the original contents of the 
In-Out Register is copied into the Accumulator. It 
happens after all normal operate class options. It 
the computer is stopped at the end of this instruction 
the Memory Buffer Register will contain zero, and the 
STsap will not yet have occurred, 

13* Clear and Complement the Accumulator (5^ sec) 
clc 

This instruction represents the or-ing of cla and cma. 
It clears (sets equal to plus zero) the contents 
of the Accumulator and then complements (changes all 
ones to zeroes and all zeroes to ones) the contents 
of the Accumulator. 



-21- 

Z&X* IK-OUT TRANSFER GROUP (5 ^sec without in-out wait) 

lot Operation Code 72 

The in-out transfer command is used to perform all the 

in-out control and information transfer functions. 

The address of the lot instructions is used to 

select various devices*, The decoding for the 

instructions is as follows : 

Bits Use 

0-4 11101 instruction bit code for 

in-out transfer 
5 Used for device synchronisation 

7-11 Useful for modification of lot 

instructions 
12-17 Addresses 1 of 64 possible device 

NOTE; Quite often, input --output operations must be 

synchronized. That is, information is transferred 

which may cause the computer (or device) to "wait", 

and then proceed in synchronism. When several 

in-out devices operate simultaneously, the synchronization 

is essential* The control for this is coded in each 

in-out transfer command. 

IK-OUT TRANSFER Wait for Completion Pulse Enable/Disable 
Command Bits for Restart/Continue Completion 

5 without wait (Done) Pulse 

Signa 1 

continue, no wait msable 

1 t*ait, then continue Enable 

Bit 5 of the in-out transfer command designates 
whether the program is to wait for a completion 
pulse before continuing and whether the completion 
pulse return signal is to be enabled or disabled. 



-22- 

The description of each in-out Instruction below Is divided 
into two parts, NON-TS and TS, so that the user can understand 
the differences . Generally, in time sharing mode the executive 
routine puffers characters for the typewriter, punch, and 
reader so the user does not worry about synchronization. 
Almost all lot instructions trap to the executive routine 
where they are interpreted and serviced* Control is 
ciuickly returned to the user's program except when an output 
instruction would cause sen overflow of an executive routine 
buffer. In this case, the program is dismissed and remains 
inactive until the buffer becomes almost emp$y. 

A* j Reader 

The perforated tape reader of the FDP-i Is a photoelectric 
device capable of reading 320 or 640 lines per second, 
Three lines form the standard 18-bit word when reading binary 
punched 8~hole tape. Five, six, and seven-hole tape may 
also be read* 

1* Read Paper Tape, Alphanumeric 
rpa Address 0001 

a. MOMS: This Instruction reads one line of tape 
(all eight channels) and transfers the resulting 
8-bit code to the Reader Buffer, (HG0?E: rpa is 
Initial^ defined as 730001 in ID symbol table 
and certainly symbol table* 
1* If bit 5 of the rpa instruction Is a -"l" 
[730O01»(rpa)3 the 8-bit code read from 
tape Is automatically transferred to the 
10 register via the Reader Buffer and 
appears as follows: 

10 BITS 10 11 12 13 14 15 16 17 
TAPE GHAEHBLS 8765 4321 
The remaining bits of the 10 are set to zero. 
The program waits until the material has been 
read and transferred and a completion pulse 
returned before continuing* 



~23- 

2. If bit 5 of the rpa instruction is a zero [ (rpa-i^jaGQGil, 
the contents of the Reader Buffer- must be transferred to 
the 10 Register by executing a rrb instruction . Vlhen the 
Reader Buffer has information ready to be transferred 
to the 10 Register, Status Register bit i is set to one, 
(Sequence break can be used in this situation to perform 
the read. ) 
b. TS: The reader must be assigned to the user*s console before 
his program can execute a rpa instruction, (Khen the 
reader is not assigned, the rpa instruction is an illegal 
one. ) The instruction is the same as in NON-TS but the 
the line read is put into a pseudo reader buffer (prb). 
The executive reader buffer routine is then filled with 
succeeding lines of tape. The contents of the prb is 
then placed in the 10 if the instruction was a rpa. 
Otherwise, on arpa-i, the material goes into the prb 
but isn't transferred to the 10 until a rrb instruction 
is executed by the user. Material is taken from the 
reader buffer in the executive routine on the next rpa 
instructions. When the buffer is almost empty more tape 
is read in to refill it. NOTE: The code of the off-line 
tape preparation typewriter (Friden FIO-DEC Recorder - 
Reproducer) contains an odd parity bit. This bit may 
bit may be checked be read-in programs. The FIO-DEC 
code can then be converted to the Concise (6 bit) Code 
used hy the PDP-i merely by dropping the eighth bit 
(parity). A liut of characters and their FIO-PEC and 
Concise Codes can be found in the Appendix, 



■24- 



Read Paper Tape, Binary 

rpb Address' 0002 

a ° Non-TS ' This instruction reads three lines of 
tape (six channels per line) and assembles the 
resulting 18-bit word in the Reader Buffer, 
For a line to be recognized by this instruction., 
Channel 8 must be punched (lines with Channel 8 
not punched will be skipped over). Channel 7 
is ignored. The instruction sub 5137^ for 
example, appears on tape and is assembled by 
rpb as follows; 

CHANNEL 8-76541321 

LINE 1 x x I x 

LINE 2 x x x I x 

LINE 3 x x x ( x x X 

Reader Buffer 100 010 101 001 Oil 111 

NOTE: Vertical dashed line indicates sprocket holes 

and the symbol "x tt Indicates holes punched on tape- 

NOTE: rpb is initially defined as 730002 in IP 
symbol table and certainly symbol table. 

1) If bit 5 of the rpb instruction is a "1" 
[730002=rpb], the 18-bit word read from tape 

is automatically transferred to the 10 Register 
via the Reader Buffer. The program waits until 
the material has been read and transferred and 
a completion pulse returned before continuing. 

2) If bit 5 of the rpb instruction is a zero 
[rpb-I*720Q02], the contents of the Reader 
Buffer must be transferred to the 10 Register 

by executing a rrb instruction. When the Reader 
Buffer has information ready to be transferred 
to the 10 Register, status Register bit 1 is 
set to one. (Sequence break can be used in 
this situation to perform the read. ) 



.p^~ 



b. TS: The reader must be assigned to the user^s console 
before his program can execute a rpfo instruction. 
(When the reader is not assigned, rpb is an illegal 
instruction. ) This instruction is the same as in 
NON-TS but the 3 lines read are put into a pseudo 
reader buffer (prb). The executive routine reader 
buffer is then filled with succeeding lines of 
tape. The contents of the prb is then placed in 
the 10 if the instruction was a rpb. Otherwise, on 
8 rpb-i, the material goes into the prb but isn^t 
transferred to the 10 until a rrb instruction is 
executed hy the user. Material is taken from the 
reader buffer in the executive routine on the next 
rpb instructions, When the buffer is almost empty 
more tape is read in to refill it* 

3* Read Reader Buffer 
rrb Address 0030 

a. NOF-TS: When the rpa or rpb instructions are given 
with bit 5 a zero (720003 «rpa~i or 72G002=rpb-i ) 
information read from tape fills the Reader Buffer 

but is not automatically transferred to the 10 Register. 
To accomplish this transfer, these instructions 
must be fallowed by a rrb instructions „ in addition 
the rrb instruction clears Status Register bit i. 

b. TS: Same as above, but the information is stored 
in the pseudo reader buffer. It is transferred 
from there to the 10. 



-26- 

B * Perforated Tape Punch 

The standard PDP-l Perforated Tape Punch operates at a speed 
of 63 lines per second. It can operate In either the 
alphanumeric or binary mode, 

1, Punch Perforated Tape, Alphanumeric 
ppa Address 0005 

a, NON-TS: This instruction takes information from 
the 10 Register and punches one line of tape in 
the following format: 

10 Bits iO 11 12 13 14 15 16 17 
Holes 87654321 

NOTE: ppa is initially defined as 730005 in ID 
symbol table and CERTAINLY symbol table, 

1) If bit 5 of the ppa instruction is a "1" 
[730005=ppa], a completion pulse is generated 
The program waits until the material has been 
flinched and a completion pulse returned before 
continuing, 

2) If bit 5 is a zero in the ppa instruction 
[ppa -1=720005], the program is continued and 
no completion pulse will be given. In this 
case, the Status bit must be checked for, 
[Sequence break can be used in this situation 
to perform the punching]. 

b. TS: Same as above but transfers one character from 
10 to the executive routine punch buffer for transfer 
to the punch when it is ready. If the buffer is 
full, the user«s quantum ends. Bit 5 Is completely 
ignored* Time - about 500 microseconds. 

2. Punch Perforated Tape, Binary 
ppb Address 0006 

One line of tape is punched, as follows: 
10 Bits O12345 
Holes 87654321 
Hole 8 Is always punched. 

Hole 7 is newer punched. 
This instruction is like ppa in all other respects. 



-27- 

c » Alphanumeric On-Line Typewriter 

The typewriter will operate in the input mode or the output mode 

1. Type Out 

tyo Address 0003 

a. NON-TS: For each in~out transfer instruction, tyo, 
one character is typed . The character is specified 
by the right six bits of the 10 Register. 
NOTE: tyo is initially defined as 730003 in ID 
symbol table and CERTAINLY symbol table, 
i. If bit 5 of the tyo instruction is a "1" 

[730003«tyo] a completion pulse is generated* 
The program waits for the completion pulse 
before continuing. 
£. If lit 5 is a zero in the tyo instruction 
[tyo-i=720003], the program is continued and 
no completion pulse will be given. In this 
case, the status bit must be checked for. 
(Sequence Break can be used in this situation 
to perform the typing. ) 

bo TS; Same as above but places a character from 

the 10 Register into the executive routine user's 
console buffer to be printed when the typewriter 
is ready. If his buffer is full, the user's 
quantum ends. The console is placed in print status 
by the executive routine and characters are printed 
from the buffer until it is empty. Then the 
console returns to type status. Bit .5 is completely 
ignored. Time: about 500 microseconds. 



-28- 

Type In 

tyi Address 00Q4 

This operation is completely asynchronous and is therefore 

handled differently than any of the preceding in~out 

operations . 

a. NON-TS: When a typewriter key is stuck^ the 6-bit 
code for the struck key is placed in the typewriter 
buffer, program flag 1 is set, and the type-in status 
bit, bit 3* is set to one. A program designed to 
accept typed-in data would periodically check program 
flag: . or bit 3 of the status register and if found 
to be set to a one, a tyi instruction could be 
executed for the information to be transferred 
to the In-Out Register. This in~out transfer 
should not use the optional in-out wait. The information 
contained in the typewriter buffer is then transferred 
to the right six bits of the In-Out Register* 
The tyi instruction clears the type-in Status bit. 

b* TS: When a typewriter key is struck, the 6-bit 

code for the struck key is placed in the console's 
typewriter buffer, the type-in Status, bit 3* is set 
to one. (Program Flag 1 is not set when a typewriter 
key is struck. ) The tyi instruction alone can replace 
the listen loop described above to accept typed-in 
data. Executing this in-out transfer instruction 
causes a character from the typewriter buffer to be 
transferred 'to the right six bits of the In-Out 
Register. If there are no characters in the 
buffer, the program is ma&e inactive until a key 
has been struck.* Programs which perform other 
operations while waiting for type-in can use a 
check Status loop or sequence break for det^cfelng 
the striking of a key* The tyi instruction clears 
the type-in status bit. Time; about 500 microseconds,, 

* The executive routine accepts manually typed characters 
and enters then in the buffer while the console is in 

type status. If the buffer becomes filled, the type -in 

light will go out and further characters typed will be lost. 



-29- 

D* Precision CRT D isplay (type 30) 

The sixteen-ineh cathode ray tube display is Intended to 
be used as an on-line output device for the PDP-l. it 
is useful for high speed presentation of graphs, diagrams, 
drawings, and a Iphanumer lea 1 information. The unit is 
solid state, self -powered and completely buffered. It 
has magnetic focus and deflection. The cathode ray tube 
has a F7 phosphor; thus a point displayed persists for 
a relatively long time. Some other display characteristics 
are. 

1024 by 1024 addressable locations 

fixed origin at center of CRT 

Plpts 20,000 points per second 

Ones complement binary arithmetic 

Random point plotting 

Accuracy of point £3 per cent of raster size 

Baster size 9.25 by 9.25 inches* 

Resolution is such that 512 points along each axis are discernible 

on the face of the tube. 

1. Display One Point on CRT 
dpy Address CIO? 

a. NON-TS and TS: This instruction clears the light pen 
status bit and displays one point using the high ten bits 
(i.e. through 9) of the AC for the X coordinate and the 
high ten bits of the IO for the Y coordinate, Wh& AC 
and 10 remain unchanged after the dpy instruction. The 
origin "(o,o) B is at the center of the scope tube and 
(377400, 400000) is the lower right comer. 
The X bits of the instruction control the intensity: 

3 is the brightest, 1 normal, 7 barely visible and 

4 visible only to photo-multiplier tubes. 

If bit 5 of the display instruction is a one, the computer 
will wait 50 microseconds for the scope to complete before 
continuing, if bit 5 is off, the program will continue 
without waiting. The computer will not begin a dg£ until 
the previous one was completed * 



-30- 

dp£ is defined in CERTAINLY and ID with bit 5 on, i.e. 
730GO2. 

Skip on Display Lever 
sdl Address 3477 

TS onig ^is instruction skips if and only if the console 
display lever is depressed. The instruction sdl i skips if 
and only if the display lever is not depressed. When a 
console's display lever is depressed, the executive routine gives 
the program running at that console extended running time. 
This facilitates observing information on the scope. 



-31- 

E. Uffat £en (Type 32) 

NON-TS and TS: The light pen is designed to be used with the 
CRT DISPLAY TYPE 30. By "writing" on the face of the CRT, 
stored or displayed information can be expanded, deleted, 
or modified. Specifically, the scope completion pulse 
(about 50 microseconds after the last dp£ or dpy - i ) 
interrogates the light pen. If it saw light, the li$it pen 
status bit and program flag 3 are set. Note that the light 
does not have to be from the scope face. A threshold control 
for the light pen is located on the bottom of the scope tube 
cabinet. 

If a program uses dpy-i instructions and szf 3 to serve the 
the light pen, there must be at least 45 m. seconds of instructions 
between the two in order to allow time for Flag 3 to be set 
by the scope completion pulse. 



-32- 

F* Drum 

The PDP-1 drum Is a high-speed magnetic drum used for storage 
It is divided into 22 i0 fields of 4 096 words each. Words 
are transferred between the drum and the core memory under 
automatic control. The drum runs at 30 revolutions per 
second: thus, each word on the drum is available once 
every 33 i/3 milliseconds. When a drum operation has 
begun, words are transferred at a rate of 8.16 microseconds 
each. In a single operation, information can be written 
on the drum, read from the drum or both simultaneously., 
1. Brum Initial Address 
dia Address 0060 

a ° NQN-TS : This instruction causes the C(lO) 
to be sent to the drum write field buffer . 
These bits specify which field of the drum will 
be written on during the next dec instruction 
or if C (10)^^ is zero, that no write operation 
Is to occur. The ^do)^-, are sent to the 
drum initial address register to specify the 
first drum address to be transferred * 
bo Tg: The field number employed In a user 3 s 

program Is a pseudo field number unless specified 
as absolute by the sign bit being on. The 
pseudo field number is translated into its 
absolute field number and checked for validity 
by the executive routine. Time: about 150 
microseconds. The 10 Is stored in ID 3 s V 
register* Checking does not happen until dec 
is executed o 
Drum Break on Address 
dba Address 0061 
a. NSN-E£: This instruction causes the C(lO)g 

to be sent to the drum initial M&Esas reglflfiw. 
When the current drum address becomes equal 
to the contents of the initial address register, 
a sequence break request Is indicated. Bit 5 
of the- status word is set by the break, and 
is cleared by the next &g£ instruction. 



p 



-33- 

bo TS: The address given will be advanced by approximately 
50 words to allow for processing by the executive 
routine . Occurrence of the eequence break will interrupt 
the user^ s program and turn on the drum status bit* 
Time: about 200 microseconds. 

3* jDrum Count and Commence 
dec Address 0062 

a. NON-TS: This instruction causes the C{lO), ,- to be 
sent to the drum read field buffer . These bits 
specify which field will be read, or if c(ic) is 
zero, that no read operation is to occur. The C(AC) 
specify which core will be used for the data transfer?* 
CUc)^^ specify the first core memory address of 
the data to be transferred. The C(I0L ±7 specify 
the number of words to be transferred. If the C(lO) fi 
is zero, 4096 words are transferred, While the gec ~ ? 
instruction is being executed, the computer stops 
and the drum system takes full control of the core 
memory. Successive words are transferred from 
sequential locations until the operation is complete,, 
If no errors occurred during the drum operation, 
the instruction following the dec will be skippedc 
The CUC) and the C(IO) are lost during this 
operation. If both read field and write field are 
non-zero (both reading and writing operations are 
specified) the contents of memory are written on the 
write field; then the read field data are read into 
memory. The read field must not equal the write field. 
In order to avoid passing a given drum address, 
and hence losing 33 milliseconds, the dec instruction 
must be given at least 19 microseconds before the 
drum address reaches the initial address. 



„34~ 

b« TS: The field number employed in a user's program is 
a pseudo field number (unless specified as absolute by 
the sign bit being on). The pseudo field number is 
translated into its absolute field number and checked 
for validity by the executive routine . The C(AC) and 
C(IO) are preserved. Time: about 300 microseconds 
plus access and transfer time. 

4„ Drum Read Address 

dra iot 63 

a» NQN-TS : This instruction causes the current drum 
address to be read into I0g_ 1? . The parity error 
flag is read Into I0 Q J The selection error flag is 
read into 10 and the timing error flag is read into 
I0 2 ° Two cycles elapse before this information is placed 
in the 10* 

b. TS: The address read will be about 50 words in 

advance of the actual position of the durm to allow 
for processing by the executive routine . Time; 
about 100 microseconds „ 

The various error conditions are as follows: 
1* Read Error s When a word is written on the drum, its parity 
is generated and is also written on the drum. Whenever 
this word is read off the drum, a new parity is generated 
and is checked against the parity just read* A mismatch 
sets the read error flip-flop. 
2. Selection Erroff : A five-bit address can specify 32 drum 
fields out of which 23 are legal and 9 are illegal. Field 
means no selection, fields 1 through 22 are legal fields 
and 23 through 32 are illegal fields* A selection 
error flip-flop will be set if a user selects an illegal 
; field, or if the read field equals the write field* 
3- Timing Error : This error monitors the drum clock circuit 
malfunctions. The timing flip-flop will be set when (a) 
the time period between consecutive clock pulses is not 
equal to ~8,g microseconds, (b) number of clock pulses 
available on the drum is not equal to 4096, or (c) the 

reference index pulse is lost* 



■35- 



S° Buttons a nd Switches 

Pour consoles of nine buttons and nine switches each can be 
added to the PDP-i time-sharing system to facilitate the 
communication between the user and the computer. 
1. Read Buttons (iO % sec ) 

rbt Address x237 where £ x £ 3 

TS: This instruction is available only in Time-Sharing. 

The button console must be assigned to the user*s console 

[When the button console is not assigned, the rbt clears 

the 10. ] This instruction reads the value of the button 

end switches into the 10 register. The right nine bits 

of the 10 register will contain the state of the switches 

from left to right (l meaning or, meaning off); 

The resulting left nine bits of the 10 will contain the 

buttons from left to right . 

89 17 10 



Buttons switches 

The x above corresponds to bits 8-9 of the rbt instruction 
and indicates one of the four possible sets of buttons 
and switches (numbered from to 3). The instruction 
rbt (=720237) reads the lowest numbered console which is 
assigned to the user; the instruction rbt 400 reads the 
second lowest numbered console assigned to the user; 
and so on« 



-36- 



H» Knob s 

Four consoles of four analog-devices each can tie added to 
the PDP-1 time sharing system to facilitate the communication 
between the user and the computer- Two such consoles have 
been addedo Analog voltage from to -10 volts from these 
devices can be converted into a binary word which and placed 
in the 10 register. 

1. Check Knobs (25-30 K sec) 
ckn Address xx27 where £ x £ 3 

TS: This instruction is available only in Time -Sharing 
The Analog console must be assigned to the user's 
console* (wlaen the device is not assigned, the ckn 
clears the 10 • ) This instruction reads the value of 
the selected analog device into the lower 8 bits 
(bits 10-17) of the 10 register. Bits 8-9 of the 
instruction determine which of the four possible analog 
consoles numbered from to 3 is selected while bits 
10-li indicate the specific KNOB (numbered to 3 
from left to right) on the selected console that is to 
be read (Other bits are unused )c 

The instructions ckn|>720027), ckn 100, ckn 200, ckn 300, 
read the lowest numbered console assigned to the user; 
the instructions ckn 400, ckn 500, ckn 600, ckn 700 
read the second lowest numbered console assigned to the 
user; and so on. 



-36A- 

Calcomp Plotter 

0.005 inch step size 

30 inch by 120 feet maximum paper size 

LiquiC Ink and ball-point pens 

Five ink colors 

300 steps per second 

7 pen sizes. 

The calcomp plotter is activated by the instruction lot 1111 . This 
causes a one step move as specified by the 10 register which has 
the following format: 

10: 12 13 14 15 16 17 

T - r - T 



pen up a- r_ +y t— y 



pen doxm 



+X — t-—X 



It is permissable to move simultaneously in that X and Y directions 
but not to move in both X or both Y directions. The pen should not 
be lifted or lowered while it is in motion. 

There is no status bit for the plotter so it can not cause sequence 
breaks or stop the computer* Thus the program is responsible for staying 
below the 300 step per second rate. (Pen up/down operations take 
0ol second), Extennal level q2 must be assigned. 



—37- 

Sxterna 1 Register 

A l8~bit register has been added to the Time Sharing facilities 
of the PDP-1 computer to add communication between programs 
and in-out devices. This External Register can be assigned 
in two modes, shared or absolute. When it is absolutely 
assigned, only one user may have it; on shared assignment, 
it is possible for more than one user to use it. 
io Load External Register from the Accumulator (5 t\sec) 
lea Address 4677 

This instruction copies the contents of the Accumulator 
into the External Register. This instruction is available 
only in Time Sharing,, The external register must be 
assigned to the user 8 s console- [When the external 
register is not assigned, the lea does nothingo ] 
2, Load External Register from the In-Out Register (5 /(sec) 
lei Address 4577 

This instruction copies the contents of the External Register 
into the 10 Register. This instruction is available 
only in Time-Sharing. The external register must be 
assigned to the user 9 s console • [When the external 
register is not assigned, the lei does nothing, ] 
3* Read External Register into the In-Out Register (5^ sec) 
rer Address 4777 

This instruction copies the contents of the External Register 
into the 10 Register* This instruction is available on3.y 
in Time Sharing* 



-38- 

J/ Sequence Break Mode 

The purpose of the Sequence Break Mode ( or program interrupt ) 
is to allow concurrent operation of several in-out devices 
and the main program sequence. It also provides a means 
of indicating to the computer than an in-out device is 
ready to accept or furnish data* 

a* $0£bXS- : The standard one channel sequence break 
mode is the mode available in NGN-TSo Interrupt 
requests can be received from any number of in-out 
devices. Each such request sets a unique status 
bit- If the channel is free, the main program 
sequence is interrupted after completion of the 
current memory cycle and the C(AC) are automatically 
stored in memory location 0, the C(PC) in location 1, 
and the C(I0) in location 2 in memory module zero* 
The time required to accomplish this is 15^rsec. 
The C(PC) as stored in location i includes the 
state of the overflow flip-flop in bit 0, the condition 
of the extend flip-flop in bit 1, and the contents 
of the Extended Program Counter in bits 3, 4, and 5„ 
The Program Counter is then reset to the address 
0003 and the program begins operating in the new sequence „ 
At the beginning of servicing a sequence break, the 
overflow and extend mode flip-flops are automatically 
set to zero, and the sequence break hold flip-flop 
is set to 1c The program beginning at location 0003 
is usually designed to inspect the Status bits, 
through the use of the Check Status Instruction, to 
determine which in-out device caused the interrupt . A 
Jump to the appropriate in-out subroutine can then 
be executed. Each such subroutine can be terminated 
by the following instruction; 

lac 0000 /to restore the AC 
lio 0002 /to restore the 10 
Jmp i 0001 /to resume the main program 



-39- 

If sequence break mode and sequence break hold are on, the 
jmp I 1 temporarily places the computer in the extend 
mode so that a 15-bit exit address is obtained, restores 
the overflow, extend mode, and PC flip-flops to their 
previous stages (i.e. just prior to the beginning of the 
sequence brearf and turns off sequence break hold-, thus 
allowing the next interrupt request received by the system 
to be processed. Interrupt requests that occurred while 
the channel was busy set status bits, and cause interrupts 
when the channel next becomes free, The read, punch, 
typewriter, light pen, and drum are attached to the one- 
channel Sequence Break System and seven status bits are 
defined (see Check Status Instruction). Three instructions 
are directly associated with the One-Channel Sequence Break 
System on the standard PDP-1: 

Enter Sequence Break Mode 

esm Address 0055 

This instruction turns on the Sequence Break System, allowing 

automatic interrupts to the main sequence to occur. 

Leave Sequence Break Mode 

Ism Address 0054 

This instruction turns off the Sequence Break System, 

Thus preventing interrupts to the main sequence. Should 

interrupt requests occur while the system is off, the 

status bit will, nevertheless, continue to be set. 



-40- 

3» Clear Sequence Break System 
cbs Address OO56 
This Instruction clears the sequence break hold flip-flop* 

A sixteen channel sequence break system exists in time sharing * 
This system has sixteen automatic interrupt channels arranged 
in a priority chain, the lowest channel having the highest 
priority* A break to a particular sequence can be initiated 
by the completion of an in-out device, the program, or 
any external signal* Breaks cannot occur within breaksi 
they are stored and serviced after the present one is 
dismissed. If more than one break occurs at the same 
time, the break with the lowest channel member will be 
serviced first. Wcien a break occurs, the C(AC) are automatically 
stored in memory location 0, the C(PC) in location 1, 
the C(IO) in location 2, all in memory module zero and the 
number of the channel that caused the break is placed 
in the AC. The C(PC) as stored in location i includes 
the state of the overflow flip-flop in bit the 
condition of the extend flip-flop in bit 1 and the contents 
of the Extended PC in bits 3 through ±7. The program 
counter is then reset to the address 0003 and the program 

begins operating in the new sequence. For a break to occur, 
the computer must be in sequence break mode, the sequence 
break hold flip-flop must be off, and the status bit and 
the corresponding enable channel associated with this device 
mu&t be on. At the beginning of servicing a sequence break, 
the overflow and extend flip-flops are automatically 
set to zero* The program beginning at location 0003 
usually contains a dispatch table since the C(AC) 
indicates which in-out device caused the interrupt* A 
Jump to the appropriate in-out subroutine can then be 
executed* Bach such subroutine can be terminated by the 
following instructions: 

lac 0000 /to restore the. AC 
lio 0002 /to restore the'' 10 
#ap i 0001 /to resume the main program 



-41- 



If sequence break mode and sequence break hold are on, the 
Jnip i i temporarily places the^ computer in the extend 
mode so that a 15-bit exit address may be obtained, restores 
the overflow, extend mode and PC flip-flops to their previous 
stages (i.e., Just prior to the beginning of the sequence 
break), and turns off sequence break hold, thus allowing 
another interrupt to the processed » The servicing routine 
should turn off the corresponding status bit. The reader, 
punch, typewriter, light pen, drum and a set of switches 
and knobs are each assigned a unique channel in the pseudo 
16 channel sequence break system- Provision has also been 
made for the connection of a user's special external equipment 
to be two higher and the two lower priority channels. The 
channels and their corresponding 10 devices in the order 
of their priority are: 

Cfoannel Device 

High priority for user's 

1 external equipment 

4 buttons 

5 light pen 

6 type -in 

7 type-out 

10 punch 

11 drum 

12 reader 

l6i low priority for user's 

17j external equipment 

02he three instructions associated with the one channel 
sequence break system of the non-time sharing system are 
supplemented by three additional instructions in time sharing. 



-42- 

lo Deactivate Sequence Channel N 

dsc N x 100 Address 0050 + (N xlOO) 
This turns off channel N in the new mode Sequence break 
system, thus not making it possible for an interrupt to 
occur on this channel. 

2* Activate Sequence Break Channel H 
asc NxlGO Address 51+(Nxl00) 
This instruction turns on channel N in the new mode 
sequence break system, thu3 making it possible for 
an interrupt to occur on this channel. 

3* ^lear All Channels 
sac Address 5§ 

*his instruction turns off all sixteen channels in the 
new mode sequence break system, thu3 not making it 
possible for any further interrupts to occur until a channel 
is activated* 



-4 3 ~ 

K. Memory Module and Memory Extension Control 

The standard PDP-1 has a 4096, 18-bit word Memory Module, 
Additional such modules are connected to the PDP-1 for 
expanding memory capacity. A memory extension control is 
needed to expand memory in increments of 4096-word modules 
beyond the standard 4096 words. This control provides a 
single-level, indirect address mode called "extend", in 
addition to the normal multiple -level, indirect address mode 
of the standard FDP-1, During the operation of a program 
the extend or noragll mode can be selected as required through 
the use of two instructions: 

1« Enter Extend Mode (5-^sec) 
eem 770046 

HSS 5E§. §M TS: This instruction places the computer 
in the single-level, indirect address mode called 
extend" « In this mode, all memory reference instruction 
that are indirectly addressed refer to the location of 
a word which is taken as a 15-bit effective address. 
This address is contained in bits 3 through 1$ of the 
specified word. The Program Counter (PC) and the 
Memory Address Register (MA) both become 15-bit registers . 
As in multiple-level indirect address mode, the 
instructions jsp, jda, cal, and Jdp supply the AC or 
memory with the state of the overflow £Up~f lop in 
bit zero, the state of the indirect address mode (extend*!, 
norma 1=0) in bit 1, and the contents of the extended 
Puogram Counter in bit 3 througi 17. Instructions not 
indirectly addressed are executed as in the standard 
PDP-1, but refer to the 4096 words in the memory module 
designated by the program counter extension, PC bits 
3 through 5* . Only bits 6 through 17 of the extended 
Program Counter act as a counter* Therefore, unless 
a transfer of control is indicated, an instruction in 
location 7777 is followed by the instruction in location 
0000 of the same memory module, as specified by PC bits 
3 through 5. In the extend mode, the cal instruction 
uses memory location 0100 and 0101 in memory module zero. 



-44- 

2, Leave Extend Mode (5/fsec) 
lem T70D4? 

NON TS aijd S£ : This instruction places the computer in 
the multiple-level, indirect address aode called "normal" 
In this mode, the PDP-1 operates as usual and all 
addressing refers to the 4096 words in the memory module 
designated fcy the program counter extension, PC bits 
3 through 5* As in the extend mode, the instructions 
jsp, 3da, cal, and jdp supply the AC "with the contents 
of the overflow, indirect address mode, and PC flip-flops 
In the normal mode, the cal instruction uses memory 
locations 0100 and 0101 in memory module zero* 



-45- 

gheck Status 

cks Address 0033 

This instruction checks the status of various in-out devices 

and sets 10 Bit3 through 6 for subsequent program interrogation 

as follows: 

a. NON-TS ; 

12 §i£ Position Status Register De finitions 

Set to i if a light-pulse strikes 

pen 50^s after the start of a dpy, 
Set to at the start of each 
dpy instruction, 

i Set to i when Paper Tape Reader 

Buffer has information ready to 
be transferred to 10 Register, 
Set to by the reader return 
pulse or by the rrb instruction . 

2 Set to i when typewriter is free 

to receive a ty o instruction 
Set to at the start of each tyq 
instruction* 

3* Set to i when typewriter key is 

struck. 

Set to by the completion of 
tyi instruction. 

4* Set to 1 when paper tape punch 

is free to receive a ppja or gpb 
instruction c 

Set to at the start of each 
pp a or ppjb instruction. 

5* Set to i when drum address equals 

address specified by dba 
instruction 
Set to by the dec instruction 

6 Set to i on entering the Sequence 

Break Mode. 

Set to on leaving the Sequence 
Break Mode. 



-46- 



b. TS: 

10 Bit Position Status Register Definitions 

Set to 1 if a light-pulse strikes 

the pen, 5C43 after the start 

of a &>X instruction. 

Set to at the start of each dpj 

instruction. 

1 Set at 1 when information is in the 

pseudo reader buffer which can be 
read into the 10 by rga, rpb, or 
rrb. if not* "~ 

2 Set to 1 when executive routine 

can accept a character via a tyo 
trap. 

Set to when it can 9 to 

3 Set to 1 when executive routine 

can supply a character via a tyi 
trap. 

Set to when it can't. 

4 Set to 1 when executive routine 

can accept a character via a ppa or 
ppb trap. 

Set to when it can*t 

5 Set to 1 when drum break return 

occurs. 

Never set to 0. 

6 Set to 1 on entering the Sequence 

Break Mode. 

Set to on leaving the Sequence 
Break Mode. 

Additional Status bits exist in time sharing. 

They cause sequence breaks if the corresponding channel is enabled, 

but are not read by the cks instruction. 

clock Set to i if external level 4 is 

(channel i) assigned and a clock pulse occurs. 

Set to by iot 6^0 if level 4 is 
assigned. 

buttons Set to 1 when a change occurs in 

the state of an assigned button console. 
Set to by rbt instruction appropriate 
to button console on which the change 
occurred. 



M. MICROTAPE 

Mechanical operation of the tape drives 

The following state diagram shows how the drives 
are controlled. 



auto 




When a drive is off, the motors are not operating, and a tape may 
be mounted or removed, men in manual mode, the motors are under 
control of the ^fwd" and'rev" buttons. When in automatic or write 
permit modes, the motors are under control of the computer and 
the tape may be read or written under program control 

To mount a tape, press it firmly onto the left hub, 
draw the tape over the head and onto the empty reel on the right 
hub, and wind it onto that reel one or two turns by hand* 
Press the "run" button to place the tape in manual status, and 
run the tape forward foi a few seconds . 
Then press the "auto" button, followed by the "write" button if desired, 



the "run 



To remove a tape, press the "stop" button, followed by 
button. Move the tape in reverse by means of the "rev" 



button until it comes completely off the take-up reel* Press 
"stop", stop the coasting tape by hand, and remove it. 



-43- 

Assignment and dismissal of microtapes 

The arq instruction with 4423 (rat") in the accumulator 
assigns the absolute tape unit in the instruction part of the 10 
to the pseudo number (0 to 17) in the low 6 bits of the 10. 
If the low six 10 bits contain zero, the tape will be assigned to 
the first free pseudo number. Pseudo micro tape numbers are stored 
in the drum field translation table, and it is not possible to assign 
pseudo microtape n and pseudo drum field n+1. If the assignment 
is successful, the arq skips and places the pseudo number in the 
low 10, The arq instruction with 77335^ (~m£") in the AC dismisses 
the pseudo microtape number given in the low 6 bits of the 10* 
It never skips, whether the tape unit was assigned or not. An attempt 
to assign a micro sape unit will not skip if a microtape is already 
assigned to the same pseudo number. 

Operation of microtapes 

Each reel of tape has 1000 blocks of 400 words each. 

The instruction ivk n, where ivk has op code 74 and n h 
a pseudo microtape number, operates that tape unit. The core address 
of the first word of the first block is in the AC bits 3-17. The 
transfer may be in any core. Bits o and 1 of the AC are decoded 
as follows 

00 - read 
10 - write 



xl - rewind 
44 



j~~ I core address ""] 



AC 



Count 




000 Block Numbed 10 



nberj 



-49- 

The right half of the 10 gives the block number of the first block 
to h© transferred* Bits to 5 give the number of blocks. This 
number should not be greater than 40 . If it is zero, one block will 
be transferred. Consecutive blocks are transferred to consecutive 
areas in core. Block is considered to follow block 777. No block 
may be transferred partly into one core and partly into another, 
but different blocks may be transferred to different cores in the 
same operation. If all blocks are transferred successfully, the 
instruction skips, leaving the address of the last word trans ferred+1 
in the AC with bits and i unchanged, the number of the last block 
transferred+i in the right half of the 10, and zero in bits to 5 
of the 10. If an error occurs on any block, the instruction does not 
skip, the right half of the 10 contains the number of the block in 
which the error occurred, and 10 bits to 5 contain the number of 
blocks remaining, including the one that was in error. 
Furthermore, an error code is placed in the AC* 

- tape unit is not in automatic status 

1 - block cannot be found (probably bad tape) 

2 - illegal core address 

3 - check sum error (the data transfer t#ok place anyway) 

4 - mark track error (probably bad tape) 

5 - data channel error (serious hardware malfunction) 

6 - no write permit 



-50- 

IV • Instructions for Communication Between User and the Time - 
Sharing System 

The following instructions were added to the time-sharing PDP-l 
system so that the user could communicate to the system itself . 
These are available only in time -sharing mode and are transparent 
to the accumulator and the in-out register unless otherwise 
stated. All these instructions trap to the executive routine 
to the user's program upon completion of the instruction. 
1* Administrative Request 
a. arq Address 2277 

This instruction is used in the time sharing system to 
assign and deassign in-out equipment and additional drum 
fields to users, (if the device is not assigned to the 
user, the instructions corresponding to that device are 
treated as illegal.) The particular assignment or deassign- 
ment requested by this instruction is indicated by 
mnemonic codes. Concise codes for thes mnemonics are 
placed in the AC and any additional information necessary 
for the request is placed in the 10 before the arq 
instruction is executed. On the next two pages is 
the table of possible requests. 

If the assignment or deassignment of fields is successful, 
the instruction following the arq will be skipped. For 
other assignments and deassignments, the instruction 
following the a£& will" be skipped only on successful 
assignment. An assignment will be suoa^ssful if the field (s) 
or device requested is not already assigned or if the 
the assignment is already in effect. 

The instruction "arq i tt skips when and only when the 
corresponding arq does not. 



-51- 



MNEMONIC WHO 
CONCISE CODE 
CONTENTS OF 


SE 

IS 
AC 


CONTENTS 
OF 
10 


REQUEST 


~r 









dismiss reader 


r 









assign reader 


~P 






-.-.«. 


dismiss reader 


P 









assign punch 


-X 









dismiss external register 


ax 






«.«.— 


assign external register 



sx 

-cl 

cl 



k 



H 



absolutely* 

assign external register 
In shared mode* 

dismiss core 1 

assign core 1- this will 
be unsuccessful when 
no drum fields are 
available since one drum 
field is used for each 
user that has core i 
assigned, 

assign or deasslgn 
analog-to-digitai consoles « 
M is a ^-bit mask for 
consoles to be assigned 
(or left assigned * in the 
case of deasslgnment) 
to the user. 



M 



ql 
q2 

q3 
q4 

q5 
q6 

q7 

*qi thru -q7 



Assign or deasslgn button 
consoles. M is a 4-bit 
mask for the consoles to 
be assigned (or left 
assigned, In the case 
of deasslgnment) to the 
user, 

assign external level 1 



tt tt 


u 


2 


It 1! 


rt 


3 


ir i? 


it 


4 


it tt 


« 


5 


tt H 


tt 


6 


tt « 


tt 


7 



deassign external level 
1 thru 7 respectively. 



-52- 



MNEMONIC WHOSE 
CONCISE CODE IS 

CONTENTS OF AC 

-q 

~f 

f 



-If 
if 



CONTENTS 
OP 

10 



tfXlOOOQ 



af 



AxiOOOO+P 



-af 



AxlOOOO+P 



deassign all external levels 

dismiss all fields 

assign N additional 
fields In absolute mode 
to lowest available 
pseudo field numbers » 

dismiss one field 

assign, in absolute mod$, 
one field- returns with 
pseudo field Just 
assigned in high part 
of AC 

assign in absolute mode, 
absolute field A (or the 
first available field If 
A«0) to pseudo field P 
(or the fiiet available 
pseudo field if A=0), 
Return with pseudo field 
in high part of AC* 

c.ase jj.: £=x, A=0„ 
deassign pseudo field x 
and the absolute field 
assigned to it. 

deassign absolute field 
lit and the pseudo field 
assigned to it. 
£aa§_3: P=x, A«y. 
deassign pseudo field X 
and the corresponding 
absolute field y. If 
x does not correspond, 
no deassignment is done 
and the request is 
unsuccessful* 

case 4 : P«0, A=*Q. 
ita deassignment is done, 
but the request is 
successful o 



-53- 



MNEMONIC WHOSE 
CONCISE CODE IS 
CONTE NTS OF AC 

tf 



CONTENTS 
OF 

__ 10 



sf 



AxlQOOQ+P 



-sf 
xf 



P 1 X10000+P 2 



nf 



mb 



mt 



AxlOOOG+P 



-Hit 



translate pseudo field 
P and returns with its 
absolute field number 
in high 6-bits of AC. 

assign, in shared mode, 
absolute field A (or 
the first available 
field if A^O) to pseudo 
field P (or the first 
available pseudo field 
if P=0). Returns with 
pseudo field in high 
6-bits of AC. 

same as -af . 

exchange pseudo fields 
P and P so that 
they correspond to the 
other's absolute field. 
This arq does not skip. 

counts the number of 
fields assigned (shared 
or absolutely) to this 
console and returns with 
this number in high 
part of AC. 

Returns memory bound 
in AC, i.e. 1+the highest 
legal address the user- 
can reference* 

Assign absolute DECtape 
unit A (0 or l) to 
pseudo capability index 
P (1 to 17, or first 
free index if P-Q). 

dismiss pseudo DECtape 
number P. 



-54- 

2o Dismiss 

dsm Address 2377 

This instruction is available only in time-sharing so that 

a user can dismiss his program and can return control tn 

ID. ID is brought back into control and types a carriage 

return. 

3. Breakpoint 

bpt 770044 

This instruction is available only in TS. It is provided 
so that ID can insert it into the user^s program where 
breakpoints are requested for debugging. When the user 
transfers control from ID to his program, a bpt instruction 
replaces the instruction previously at the breakpoint location. 
When this instruction is encountered, ID types the address at 
which the trap occurred followed by a ")" and a tab. 
Then the previous contents of that register are typed out 
and the current location pointer is set to that address „ 
If a bpt is encountered at a location where a breakpoint 
was not assigned to the user through ID, then ID interprets 
the instruction as illegal. 

NOTE: Do not attempt to break at a program -mod if led or program- 
read instruction or at an instruction in the middle of a chain 
of indirect addressing. 

4 Wait 

wat Address 2477 

This instruction is available only in time-sharing and is 

provided so that the user may deactivate his program and 

wait until a sequence break occurs. When the break occurs, 

the contents of location 1 is the location of the wat instruction 



-55- 

V. ADDRESS MODES AND MICROPROGRAM CLASS 

Ao Address MODES 

The Index register is an active register which is particularly 
useful ?or modifying operand addresses* its name derives from 
its use in Indexing through arrays since its contents (the index) 
can be added to the address field of an Instruction (array 
base address) to determine the effective address for the desired 
operand . In dealing with linked data structures it is often 
convenient to load a "pointer" Into the Index register 
and to have a "displacement" quantity In the address field 
of the instruction . Thus the effective address becomes the 
pointer value offset by the displacement. 

On the PDP-1 the index register (XK) is an 18-bit register 
Effective address calculation is performed by one's complement 
addition of the XR and the address field of the instruction 
The result is a 15-bit extended address which is relative to 
the current core if the machine Is not in extend mode. If 
the machine is in extend mode, the 15-bit index sum is 
absolute . The indexing operation does not require any time 
in addition to the instruction time. 

Since there are no spare bits available In the op code to 

designate the indexing operation the tt %® bit (bit 5) 

is used to designate either indirection or indexing, depending 

upon the state of the machine as set by mode instructions. 

The machine remains In any given mode until another mode 

setting instruction is executed. 

Mode setting instructions are: 

1* Normal Address Mode 

nam op code 770052 

Memory referencing instructions containing an 
"i" bit will be Indirected. 
2. Index Address Mode 

lam op code 770054 

Memory referencing instructions containing an 
"i" bit will be indexed. 



-56- 

Base Address Mode 

bam op code 770053 

Memory referencing instructions, are always indexed. 
If the "i" bit is on, the instruction is also 
indirected, and indexing occurs first. 

Defer Address Mode 

dam op code 770055 

Memory referencing instructions are always 
indirected. If the "i" bit is on, the instruction 
is also indexed a and indexing occurs first. 

Alternate Add3?ess Mode 

aam op code 77OO56 

The instruction following the gam is executed 

in an address mode different from the nominal 

address mode as follows: 

nam *m» ■ «»» bam 

iam « c > dam 

If xct follows aam, the xct itself will be 

executed in the alternated mode, but the instruction 

which the xct fetches will be executed in the 

nominal mode. 

The nominal mode for the instructions jmp, jsp, 
Jdp, jda is always taken to be normal* However, 
a am will alternate the address mode. The 
effective address of cal is always 0100 in core 0. 



-57- 



Bc 



FLAG WORD 



There is an 18-bit flag word, the register "F M of ID, 
containing the following: 



bit 



1 2 S 4 



t — r 



12 17 
12 3 14 5 6 



^h 4^ 



Program Flags 



f ^Sequence break hold JL. 
—Sequence break mode 
L M1 
^EF 
AMD 
AMD and AEF determine the nominal address mode: 
AMD AEF MODE 
nam 

1 bam 

1 lam 
1 1 dam 

ML is complemented by the §ajs instruction. If AAL is on, 
the next instruction is executed in alternated address mode 
unless the instruction Is in an &q& chain and siot the first 
xct of the chain, and then AA1 is turned off. If AAL is on, 
sequence breaks will not occur • 

Read Program Flags 
rpf op code 770050 

This instruction reads bits 0-2, 12-17 of the flag 
word into the 10 and clears bits 3-11 of the ID. 



Load Program Flags 
lpf op code 770051 

This instruction loads bits 0-2, 12-17 of the 10 into the 

flag word. 



-58- 



C MICRO-PROGRAM CLASS 

The micro-program instruction class has the following 
instruction format* 

BIT t Q 1 2 3 4 5 6 7 8 9 1 U 12 14 15 17 

Ts s \ 



inst. part 
(=77) 




skip condition 



operands 

specifies a column 
in the chart below 

operation 

specifies a row in the chart below* 



assignment of result 



XX 



000 

001 
010 
011 
100 
101 

110 

111 



symbolic specification for Micro-program operations 
A =AC, I = IO, X » XR 



TI 



CI 



I 

Gv*i) 



AMI 



2 
(zero) 



SA 
(AC) +1 



[IOJ +1 



SX 
(XR) +1 



AVI 
MI 



ii-T. 



A+I 



TA 



CA 



A 

(X-»A) 



XMA 



XVA 



XAA 



***& 



X+A 



•Anw 



TX 






A 
(X-*l) 




XAI 



T*T 



X+I 



t 



S (Step, ie., add one) 



OPERATION (result) 

T (True, test, or transfer) 

C (Complement (negative)) 

exchange (see explanation 
below) 

■M (arithmetic Minus) 
V (inclusive OR) 
A (Bitwise AND) 

~ (exclusive OR) 
+ (arithmetic Plus) 



-59- 



The functions of the. result assignment and skip condition 
fields are as follows: 

AAA Bit 11=1 will put the result in the AC 
Bit 12=1 " l? M " « !l 10 
Bit 13-1 " " n " " H XR 

SSSSi Bit 14=1 will cause a skip if the result is >f-0 
Bit 15=1 w " u " " " » " <~Q 
Bit 16«1 n ii n n .» « ,« « ^ +Q 

Bit 17=1 " fl " " " " H " « -0 

The execution of micro-program instruction computes the result 
specified by the XX and IYY bits (i«e. from Table on previous page), 
puts this result in the specified register (s) and skips if any 
of the specified conditions are true. Note that skip condition 
is evaluated on the result of the micro-program, not the final 
contents of any given register, and the result need not be 
assigned to any register. Thus, it is possible to test the sum 
of the AC and 10 to see if it is equal to -0 or greater than +0 
without destroying the contents of these registers. The instruction 
to do this is 773611 or, symbolicly, A+UYI>. All opr i instructions 
take 5 seconds * 

The "T JI operation clears the transmitted register after the 
transfer. This may be prevented by assigning the result back to 
the transmitted register. See the examples. 

The exchange operation is a special case. The result I (A-»l) 
means that the result of the function is the old 10 register, 
but in addition the accumulator is placed in the 10- This secondary 
assignment is done before the assignment given by the AAA bits 
in the instruction. Thus, the instruction A->I (772400) will move 
the AC to the 10, A^IA (77*500) will swap the AC and 10, and 
A-*II (772440) does nothing (because the primary assignment is to 
the 10 and the result is the old 10 )• 



-60- 

If the result of an add or subtract micro-program instruction 
is zero, the result is +0 except in two cases: 
(-0) + (-0) » (-0) 
(-0) - (+0) - (-0) 

The step instructions steps (-i) to (-f0)» 

Micro-program instructions never turn on the overflow flip-flop, 



USAGE 

The assembler considers certain symbols consisting of capital 
letters as micro-program instructions. The entire instruction 
must be in upper case, and may appear in any expression, e.g., 
storage word, constant, etc, When typing into ID the instruction 
must be preceded by a sing3.e quote (»'). 

Micro-programs are specified by concatenating three "fields" 
- the result field, the assignment field, and the skip field- The 
characters in all of these must be in upper case and there must 
be no separator between the fields. 

<result fieldXassignment fieldXskip field> 

<result field> must be one of the twenty-eight results given 

in the Table on a previous page. 

<assignment field> may be null (no characters) o: any combination 

of -&, I, and X to specify in which registers 
the result will be placed » 

<skip fieid> may be null or contain any combination of 

>, <, P, M, |, _, and ^. 

> means skip if result is greater than +0 
P means skip if result is equal to +0 
M means skip if result is equal to -0 
< means skip if result is less than -0 
| means complement the specified skip conditions 
« and _ means skip if result is either +0 or -0 

Since the octal representation of a micro-program instruction 
is computed by eaelusive - OR 3 ing all of the specifications 

within each field, redundant specifications may lead to unexpected 

results . 



-61- 

For example TAIII is the same as fll; and TAI» is the same as TAI. 
An error in syntax results in a uer error message from the assembler, 

MICRO-PROGRAM INSTRUCTION GLASS 



action 

computes, sum of AC and 10 and does nothing at 
all with it. 

the sum of the AC and 10 is put into the AC. 

the sum of the AC and 10 is put into the AC, 
10, and XR, 

skips if the sum of the AC and 10 is less than 
-0 or equal to +0. 

skip if the sum of the AC and 10 is not 
less than -0 or equal to +0, 

the sum of the AC and 10 is" put into the XR. 
If the sura was -0, +0, or greater than +0, 
the instruction, will skip. 

exchanges the 10 and XR. The "old" 10 is 
also put into the AC. This instruction 
skips always* 

the AC, 10, and XR are cleared. 

skip if the AC plus one is greater than +0* 

add one (step) to the AC and skip if it is +0. 

skip if the XR is -0 and clear the XR. 

skip if the XR is -0. 

transfer the contents of the AC into the 
XR and 10, the AC is cleared. 



Sample Micro 


-program 


symbolic 


octal 


A+I 


773600 


A+IA 


773700 


A+IAIX 


773760 


A+I<P 


773606 


A+I<P| 


773611 


A+IX£ 


773633 



X-»IXA| 



776437 



ZAIX 


77H60 


SA> 


771210 


SMf 


771302 


TXM 


776001 


CXP 


776202 


TAXI 


77^060 



TAAXI 



774160 same as TAXI, but the AC Is not cleared. 



~62~ 

EXAMPLES: 

Program which stores zeroes in all of array2» 

n*=lQ0 

dimension array2 (n) 

iam /enter indexing mode 

Ixr (~n /initial value into XR 

dzm i array2+n /store a zero into the array 

SXXP /step xr and skip if it is +0 

jmp .-2 /continue loop 

/that does it. 

To restore address mode after sequence break service, 
assuming sb service is in nam or iam* 



lxr 


XR 


/saved XR 


lac 





/saved AC 


lio 


fig 


/saved flag word 


Ipf 






ril 


1 




spi 






ema 




/undo bam or dam 


lio 


2 


/saved 10 


Jrnp i 


1 


/dismiss 



~63~ 
ADDITIONAL NOTES 



1* Due to hardware changes which are in progress, the time 
estimates given in this list may be wrong. In general it 
is very difficult to say how long a sequence of instructions 
will take to execute — in time -sharing, it is impossible - 

2. No attempt has been made to deseirbe the ijk, (7^0000) 
instruction or the I/O Function bus because most I/O 
devices are still operated by iot instructions, 

3* Defer address mode (see d am ) will be changed in the future.